Am using 180nm UMC process to draw schematic of a CMOS Inverter and do its layout using Virtuoso by Cadence Design Systems.
1) Draw the schematic of the CMOS inverter in Virtuoso Schematic Editor as shown in the attached image. Make sure to add the pins with their correct directions. sometimes the supply pins should be inout whereas sometimes in pins are accepted. Do not add any supply or anything which is not usually fabricated on silicon.
2) Make a symbol if required ( usually a good idea since it allows easy instantiation)
3) Open schematic with schematic on screen and click TOOLS > DESIGN SYNTHESIS > LAYOUT XL
4) A new window pops up “Startup Options”. Choose “create new” and click OK
5) Give layout name in the next window
6) Now two new windows open
⁃ LSW or Layer selection window
⁃ Virtuoso XL layout editor
7) In layout window DESIGN > GENERATE FROM SOURCE
8 ) Select master layer as ME1. this is the layer to which the pins belong. click OK. Now we should see the transistors and the 4 pins and a boundary. if the transistors are overlapping then separate them out.
9) Alternate way is to first select all components in schematic and in layout editor CREATE > PICK FROM SCHEMATIC. here we need to manually draw the prboundary from LSW. draw it with suitable size in the first quadrant of the layout editor space.
10) Separate the devices and the pins and place them inside the boundary.
11) We can also place the pics like in schematic by, PLACE > PIN PLACEMENT > SCHEMATIC VIEW.
12) Click SHIFT + F to get layers in layout and CTRL + F to hide them.
13) Before drawing layers we should decrease the minimum mouse movement to get small shapes. Do this from, DISPLAY > OPTIONS > change x y snapping value to 0.0001
14) Now draw the required layers from CREATE menu like interconnecting poly, metal routing etc. Use PO1 as poly layer and ME1 as the metal layer. First select the layer in LSW then select the shape in Layout window and then draw.
15) The size of any shape can be altered by first not selecting anything, then press S and then rover the mouse over the edge to be extended or reduced, then move mouse and again click when required size is achieved.
16) If the pins are not in layer ME1 then change the layer by selecting the pins and press Q to query them.
17) To create body connection for PMOS, create an M1 – NWell contact near the PMOS and simple connect this contact to VDD. this is cause the body to be connected to Vdd. After making the NWell contact, enclose the PMOS and its body contact in a rectangle of layer NWELL from LSW.
18) Body connection of NMOS can be obtained by making a M1 – PDIFF contact nest the NMOS. here we do not need to make any well outside the device since am using NWELL process.
19) Note that in neither of the devices, the body contact make near the device has to be connected to the device. they are automatically connected.
20) You can also keep a track of the connections by getting fly lines from CONNECTIVITY > SHOW INCOMPLETE NETS
21) The UMC process which am using does not support Pins to pass DRC and LVS. Hence here we need to remove the pins and simply add suitable labels to the net.
22) When Layout complete, Run DRC and remove any errors which come. After DRC run LVS and remove any errors if present.
NOTE : If layout is once closed and opened again, the fly lines vanish. To get everything like before, click, TOOLS > LAYOUT XL in layout editor window. the schematic will reappear and things will be like before.
NOTE : If DRC and LVS pass without errors, means we can go ahead with RC extraction. Our layout is error free.
(Images Coming Soon…..)