NIT Durgapur, INDIA
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Cadence Tutorials

By Dr. Rishi Todani
Under the guidance of Dr. Ashis Kumar Mal and Dr. Rajib Kar

Cadence Training

Virtuoso Schematic Editor
Simulation using Spectre
Basic and Advanced Analysis
Custom Layout Design
IO Pad Ring Layout
GDSII Generation

Cadence Introduction

Cadence environment
Operating System
Setting it up

Simulation Tutorial

Basic Simulation: DC, AC and Transient
Advanced Simulation includes
Noise analysis, THD, IP3, Montecarlo

Layout Tutorials

Layout of CMOS Inverter
Layout of Pad Ring structure
Good layout practices

 Two Chips Taped-Out
UMC 180 nm CMOS Technology

Sixth Order Switched Capacitor Chebyshev Low Pass Filter For Bio-Medical Application
Non-Overlapping Clock Generator Using High Delay Inveted Inverter For Biomedical Application and PDM Based Opamp

Die Photographs
First Tapeout using UMC 180 nm CMOS Technology

6th Order Switched Capacitor LPF

For Biomedical Applications


100 Hz – 1 dB max
220 Hz – 40 dB min
Max Power 0.18 mW

6 Folded Cascode Opamps

Fully differential folded cascode structure  designed using Potential Distribution Method (PDM)

Buffer Stages for Driving Package Bonding Wires

Unity feedback folded cascode stages for driving bonding wire inductance and pad pin capacitance.

On Chip Non Overlapping Clock Generator

Includes an indegenious extremely slow delay block (Inverter Inverter). Optimizes circuit for power and area

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